1. Field of the Invention
The present invention relates to a method of fabricating a dual damascene structure, and more particularly, to a method of fabricating a dual damascene structure adopting the double patterning technique (DPT).
2. Description of the Prior Art
In the fabrication of semiconductor integrated circuits (ICs), semiconductor devices are generally connected by several metallic interconnecting layers commonly referred to as multi-level interconnects, and a damascene process is a convenient and predominant method for forming the multi-level interconnects. Principally, the damascene process includes etching a dielectric material layer to form a trench and/or via patterns, filling the patterns with conductive materials, such as copper, and performing a planarization process. This way, a metal interconnect is obtained.
With the continuous miniaturization of the semiconductor devices and the remarkable advance in fabrication techniques of semiconductor devices, the double patterning technique (DPT) has been developed and taken as one of the most promising lithographic technologies for 32 nanometer (nm) node and 22 nm node patterning processes to overcome the limitations of the conventional tools. The litho-etch-litho-etch (LELE) approach, also called 2P2E, is one of the most common DPTs for fabricating patterns in a semiconductor device. For example, when a 2P2E approach is carried out, the first pattern can be formed in the target layer, such as a dielectric material layer, through the first lithography process, and subsequently, the second lithography process is performed to form the second pattern in the target layer. Accordingly, complicate and intensive patterns are defined in the specific region of the target layer.
However, after the first lithography process, the target layer having the first pattern formed thereon may directly contact the cleaning solution, the etchant or the chemical solvent used in the second lithography process, and the formed first pattern in the target layer may be deformed or the exposed surface of the target layer may be damaged, which may reduce the correctness of the formed first pattern and adversely affect the later manufacturing processes. For example, in the damascene process of the metal interconnect, the openings of the first pattern may not be capable of being filled with the conductive material and voids may be formed between the conductive material and the target layer due to the deformation of the first pattern, and the yield of the later formed semiconductor devices decreases.
Consequently, how to improve the patterning process for obtaining complete patterns is still an important issue in the field.